Tramplin Electronics Vacancies
RTL Design Engineer
LTD “Tramplin Electronics” is engaged in the development and production of licensed processors, microcontrollers, electronic components, and other high-tech radio-electronic solutions. The company ensures technological independence by organizing a full-cycle production of microprocessors.
We are seeking an expert to develop RTL design for new functionality and integrate existing intellectual property.
Responsibilities:
- Develop and debug complex functional blocks for ASICs in Verilog/SystemVerilog
- Participate in writing test plans
- Develop detailed design specifications and documentation
- Assess and optimize PPA (Performance, Power, Area)
- Create timing constraint files for functional and test modes
- Maintain the existing codebase
Requirements:
- Higher technical education
- At least 3 years of RTL (register transfer level) development experience
- Completed projects
- Proficiency in Verilog/SystemVerilog
- At least 3 years of using an RTL simulator experience (preferably Synopsys VCS)
- Experience of working with synthesis (preferably Synopsys Design Compiler)
- Knowledge of modern processor architectures and contemporary SoC interfaces (ACE, AXI)
- Using Linux experience
- English language skills sufficient for reading technical documentation and technical correspondence
- Experience in working with version control systems
You Might Thrive In This Role If You Have:
- Proficiency in scripting languages: Python, Bash, TCL
- Experience in working with FPGA
- Basic knowledge of C/C++
- Verification of complex functional blocks experience
Conditions:
- Official employment under the Labor Code of the Russian Federation
- Working hours from 9:00 to 18:00. First three months in the office. You may to adjust starting time. Afterwards a hybrid work arrangement may be available: four days in the office and one day remotely.
- Office is near Nagatinskaya and Kolomenskaya metro stations
- Voluntary health insurance after the probation period
- Salary: 250,000–350,000 rubles per month after negotiations
Please, send your resume to:
ASIC Physical Design Engineer
LTD “Tramplin Electronics” is engaged in the development and production of licensed processors, microcontrollers, electronic components, and other high-tech radio-electronic solutions. The company ensures technological independence by organizing a full-cycle production of microprocessors.
We are seeking a specialist for physical design of FPGA/ASIC projects from RTL to GDSII.
Responsibilities:
- Maintenance, modification, and documentation of the design flow
- Floorplanning, placement, and routing at block and chip levels
- Analysis of results (timing, power, area) and feedback to RTL engineers
- Write block timing constraint files for functional and test modes in collaboration with RTL engineers
- Physical verification and finish work prior to tape-out
Requirements:
- Higher technical education
- At least 3 years experience in ASIC physical design
- Completed projects
- Knowledge of the ASIC physical design flow from RTL to GDSII
- Experience in working with logic synthesis (preferably Synopsys Design Compiler)
- Experience in working with ASIC place-and-route EDA tools (preferably Cadence Innovus)
- Experience in working with ASIC physical verification EDA (preferably Mentor Calibre)
- Experience in working with static timing analysis EDA (preferably Synopsys PrimeTime)
- Experience of using Linux
- English language skills sufficient for reading technical documentation and technical correspondence
- Experience in working with version control systems
You Might Thrive In This Role If You Have:
- Proficiency in scripting languages: Python, Bash, TCL
- Experience in working with FinFET technologies
- Knowledge of DFX methodologies
Conditions:
- Official employment under the Labor Code of the Russian Federation
- Working hours from 9:00 to 18:00. First three months in the office. You may to adjust starting time. Afterwards a hybrid work arrangement may be available: four days in the office and one day remotely.
- Office is near Nagatinskaya and Kolomenskaya metro stations
- Voluntary health insurance includes dental, hospitalization, psychologist, check-ups, oncology insurance — after the probation period
- Salary determined by interview results
Please, send your resume to:
15.01.2026
Digital Design Verification Engineer
LTD “Tramplin Electronics” is engaged in the development and production of licensed processors, microcontrollers, electronic components, and other high-tech radio-electronic solutions. The company ensures technological independence by organizing a full-cycle production of microprocessors.
We are seeking a specialist for RTL design verification of new functionality and testing the integration of existing IP.
Responsibilities:
- Develop and maintain UVM environments for complex functional blocks
- Write test plans for complex functional blocks
- Develop, debug, and maintain test benches for digital logic blocks
- Writing system integration tests of complex functional blocks
- Integrate VIPs into test environment
- Collect and analyze test coverage, refine test plans based on results
- Plan testing of IP on FPGA prototypes
- Verify logical equivalence between RTL and physical design results
- Conduct regression testing
- Collaborate with engineers, who are responsible for RTL design of complex functional blocks and IP
- Document test environments
- Maintain existing test environments
Requirements:
- Higher technical education
- At least 3 years experience in design or testing of complex functional blocks
- Completed projects
- Knowledge of SystemVerilog/Verilog
- At least 3 years experience of using RTL simulator (preferably Synopsys VCS)
- Knowledge of RISC assembler (any instruction set architecture) and C
- Understanding of digital design principles
- Experience in using Linux
- Proficiency in English for reading technical documentation and technical correspondence
- Experience in working with version control systems
You Might Thrive In This Role If You Have:
- Knowledge of formal verification methods
- Experience of working with continuous integration (CI) systems
- Knowledge of cocotb
- Knowledge of scripting languages (Python, Bash, TCL)
- Knowledge of SystemVerilog Assertions
Conditions:
- Official employment under the Labour Code of the Russian Federation
- Working hours from 9:00 to 18:00. First three months in the office. You may to adjust starting time. Afterwards a hybrid work arrangement may be available: four days in the office and one day remotely.
- Office is near Nagatinskaya and Kolomenskaya metro stations
- Voluntary health insurance after the probation period
- Salary: RUB 150,000 – 300,000 per month, based on interview results
Please, send your resume to:
19.01.2026